The present invention relates to semiconductor integrated circuits and their manufacture. The invention is illustrated in an example with regard to the manufacture of a read only memory cell, and more particularly to the manufacture of a voice read only memory cell which is coded before metallization, but it will be recognized that the invention has a wider range of applicability. Merely by way of example, the invention may be applied in the manufacture of other semiconductor devices such as mask ROMs, among others.
Read only memories (ROMs) and various methods of their manufacture are known in the art. In the fabrication of a ROM, it is necessary to fabricate a storage cell that maintains data after the applied power is turned off, that is, a storage cell having almost permanent data characteristics. The storage cells are generally mass data storage files where each cell corresponds to the presence or absence of a transistor. Data is programmed into the cells during their manufacture. The process of programming data is often called coding. Examples of cell coding methods include field oxide programming, implant programming, and through-hole programming.
Field oxide programming provides for two types of metal oxide semiconductor field effect transistors (MOSFET) by the use of different gate oxide layer thickness for each transistor type. Each oxide layer thickness corresponds to a different transistor threshold voltage. In programmed cells, the thickness of the gate oxide layer is about the same thickness as the field oxide, thereby providing a transistor which is permanently "off" or in a logic "0" state. Unprogrammed cells include typical thicknesses for the gate oxide layer so that the transistor is "on" or in a logic "1" state. A disadvantage of the field oxide programming method includes a longer product turn-around-time (TAT) as measured from the programming step. Much of the process occurs after programming the gate oxide layers of the cells.
Another programming technique is the threshold voltage implant method which changes the transistor threshold voltage by ion implanting the transistor gates for programmed cells. In n-channel devices, impurities such as boron are implanted into exposed gates which raise their threshold voltage. The implant forces the gates of the cells permanently to an "off" state. Unexposed gates are not implanted and therefore provide cells at an "on" state. Heavy implants, however, often create damage to the thin gate oxide region. Damage to the gate oxide region causes higher parasitic junction capacitance between the source (or drain) and channel region of the metal oxide semiconductor field effect (MOS) transistor. Higher parasitic junction capacitance leads to an increase in average word-line capacitance, and often results in slower speeds.
A further method of ROM programming includes selectively opening the contact holes for each transistor to drain. Such method called the through-hole contact programming technique was, in fact, the historical ROM programming method. The through-hole contact programming technique, however, requires a contact for every cell, thereby increasing the size of the cell array. Increasing the size of the cell array often provides a resulting device which has a lower cell density. Lower cell density typically corresponds to higher integrated circuit costs, and less memory capacity which is incompatible for the higher memory ROM devices.
It is often desirable to apply the ROM code onto the partially completed devices during a latter part of the manufacturing process. By applying the code at the latter process, it takes less time to process the wafer from that point to completion. Less time for completion corresponds to a faster product turn-around-time. As the life cycle of integrated circuits become shorter, it is typically desirable to fabricate products with shorter turn-around-times.
Industry relies on two general types of ROM array structures and combinations thereof using cells fabricated by the described methods. Such array structures include the serial ROM cell structure which is a NAND gate type structure and the parallel ROM cell structure known as the NOR gate type structure. Characteristics of NOR and NAND gate type structures are often competing.
A parallel NOR gate type structure includes a set of MOS transistors connected in parallel to the bit-line. The parallel structure typically increases the speed of the ROM but decreases bit or cell packing density. The lower density is caused by the use of a larger cell size. The larger cell size exists from the contacts needed for each cell.
Alternatively, a serial NAND gate type structure often increases cell packing density or bit density but provides a slower operation speed. The serial structure forms a denser structure since no contact holes are required. Higher memory requirements for state-of-art devices use the denser serial NAND gate type structure.
Still further, competition in the semiconductor industry creates a need for products having identifiable features for the purpose of recognizing chip piracy. Piracy of semiconductor designs tends to increase as world-wide demand for semiconductor chips grows. However, it is often difficult to determine whether a competitor's chip has been copied or actually infringes a patented process or structure without extensive investigation. Accordingly, it is desirable to manufacture a semiconductor chip with features therein for easy identification.
From the above it is seen that a method of fabricating semiconductor ROM devices that is easy, reliable, cost effective, and identifiable is often desired.